Assignment 2 ALU Lab Report
4 bit way multiplexer
For this program, the IEEE library was used in order to use all the functions ALL module in the STD 1164 logic.
The entity I developed is the mux_2tol_top by name.
The selection the port in the 4 bit and named them SEL, A, B, X (with X as the output).
The architecture used is Behavioral for the entity developed above. In this architecture, the output is A when the STD Logic (SEL) is equal to 1, otherwise, it takes the value of B.
2 bit way multiplexer
The 1 bit ALU consists of a single module in VHD which takes in 3 inputs and one output.
It performs the ‘or’ operation on the three inputs before it begins to ensure valid inputs, then it performs the operation which is usually supplied in binary.
If the binary code is 00, then an ‘and’ operation is performed on the two inputs.
If the binary code is 01, then an or operation is performed on the two inputs.
If the binary code is 10, then an addition is performed on the two inputs.
If the binary code is 11, a subtraction operation is performed on the two inputs. Otherwise, the output is set to the 1’bx value.
The outputs of the above operations are stored in the output variable ‘out’.
This counter uses the IEEE library too in order to access the numeric and logic modules of it.
An entity count is created. In this entity, a port is created and set to clock, reset, enable (all take in standard logic), then q which is the output as an integer in the range of 0 to 255 or(28 numerals starting from 0).
An architecture follows which is named rtl of the architecture above.
The ‘clk’ (clock) is processed and a variable is created to store the integers in the range mentioned above.
In the process, if a rising edge of the clk is observed;
- If the reset is ‘1’ then the count is set to zero.
- Else, if the enable is ‘1’ then the count is incremented by 1.
Finally, the output q is set to the counter and the process ends, followed by the end of the architecture.
The 4 bit ALU for Arithmetic Operations
This ALU does not differ much with the previous 4 bit ALU arithmetic, except that it uses four bit binary digits as their operation cases.
An example is the , 2’b0000 to represent an and operation, and 2’b1000 to represent the subtraction operation.